High switching trench mosfet

ABSTRACT

A shielded gate trench metal oxide semiconductor filed effect transistor (MOSFET) having high switching speed is disclosed. The inventive shielded gate trench MOSFET includes a shielded electrode spreading resistance placed between a shielded gate electrode and a source metal to enhance the performance of the shielded gate trench MOSFET by adjusting doping concentration of poly-silicon in gate trenches to a target value. Furthermore, high cell density is achieved by employing the inventive shielded gate trench MOSFET without requirement of additional cost.

FIELD OF THE INVENTION

This invention relates in general to semiconductor devices, and moreparticularly, to an improved and novel device configuration forproviding a metal oxide semiconductor field effect transistor (MOSFET)with high switching speed.

BACKGROUND OF THE INVENTION

Compared to a conventional trench metal oxide semiconductor field effecttransistor (hereinafter MOSFET), a shielded gate trench MOSFET is moreattractive due to its reduced Cgd (capacitance between gate and drain)in accordance with reduced Qgd (charge between gate and drain), andincreased breakdown voltage of the trench MOSFET, making an excellentchoice for power switching applications such as inverter and DC to DCpower supply circuits. However, for those power switching applications,MOSFET body diode reverse recovery charge is very important due to thefact that high body diode reverse recovery charge value increasecomplimentary MOSFET turn-on loss, which pronounces especially when theshielded gate trench MOSFET is used for the low-side switch.

FIG. 1A shows a shielded gate trench MOSFET 100 disclosed in prior artU.S. Pat. No. 7,768,064 comprising a resistive element 101 betweenshielded electrode 102 and source metal for reduction of the reverserecovery charge of a parasitic body diode in the shielded gate trenchMOSFET 100. Besides, the shielded gate trench MOSFET 100 furthercomprises: a planar source-body contact to contact n+ source region 103and P body region 104 with the source metal 105; and a p+ ohmic bodycontact doped region 106 to reduce the contact resistance between thesource metal 105 and the P body region 104.

From FIG. 1B which is a top view of the shielded gate trench MOSFET 100,it can be seen that, the resistive element 101 (illustrated by dashlines) is placed between end contacts 106 and 107, wherein the endcontact 106 is connected to the shielded electrode 102 (as shown in FIG.1A) while the end contact 107 is connected to the source metal 105.However, according to the prior art, the resistive element 101 isimplemented by poly-silicon, diffusion or other suitable material aslong as the resistive element 101 is greater than overall distributionor spreading resistance of the shielded electrode 102, therefore, theimplementation of the resistive element 101 will need additional costsuch as additional mask for poly-silicon resistor. Moreover, if theresistive element 101 is made of diffusion such as n+ source, anadditional parasitic bipolar will be introduced degrading in thebreakdown voltage.

Furthermore, the shielded gate trench MOSFET 100 used planar source-bodycontacts as shown in FIG. 1A, resulting in difficulty for cell pitchshrinkage.

Accordingly, it would be desirable to provide a new and improved powersemiconductor device, for example a shielded gate trench MOSFET havinghigh switching speed and high cell density without requirement ofadditional cost.

SUMMARY OF THE INVENTION

It is therefore an aspect of the present invention to provide a new andimproved power semiconductor device to solve the problems discussedabove. According to the present invention, there is provided a powersemiconductor device comprising: a plurality of gate trenches extendinginto a silicon layer of a first conductivity type; a gate electrodedisposed in upper portion of each of the gate trenches and a shieldedelectrode disposed in lower portion of each of the gate trenches,wherein the gate electrode and the shielded electrode insulated fromeach other by an inter-electrode insulating layer; the gate electrodeand the shielded electrode are doped poly-silicon layers wherein thegate electrode having doping concentration equal to or higher than theshielded electrode; the gate electrode connected to a gate metal througha gate electrode spreading resistance and the shielded electrodeconnected to a source metal through a shielded electrode spreadingresistance; and the upper portion of the gate trenches surrounded bysource regions of the first conductivity type and body regions of asecond conductivity type in active area.

By providing a power semiconductor device, for example a shielded gatetrench MOSFET according to the present invention, the shielded electrodespreading resistance replaces the resistive element in the prior art byadjusting doping concentration of the poly-silicon in the gate trenchesto a target value. Therefore, no additional cost will be added and noany drawback is introduced, enhancing the performance of the shieldedgate trench MOSFET.

In another preferred embodiment, the power semiconductor deviceaccording to the present invention further includes one or more detailfeatures as below: the gate electrode spreading resistance is lower thanthe shielded electrode spreading resistance; the power semiconductordevice further comprising a first gate oxide along sidewalls of the gateelectrode and a second gate oxide surrounding bottom and sidewalls ofthe shielded electrode in each of the gate trenches, wherein the secondgate oxide having oxide thickness thicker than the first gate oxide; thepower semiconductor device further comprising a plurality of source-bodycontact trenches formed between two adjacent of the gate trenches andpenetrating through a contact insulating layer and the source regionsand extending into the body regions; the power semiconductor devicefurther comprising a plurality of source-body contact trenches formedbetween two adjacent of the gate trenches and penetrating through acontact insulating layer, the source regions and the body regions andextending into the silicon layer; the power semiconductor device furthercomprising a tungsten layer padded by a barrier layer filled into eachthe source-body contact trench for contacting the source regions and thebody regions along sidewalls of the source-body contact trenches, andthe tungsten layer electrically connected to the source metal; the powersemiconductor device further comprising an anti-punch through region ofthe second conductivity type surrounding sidewall and bottom of each thesource-body contact trench below the source region; the tungsten layeris only filled within each the source-body contact trench but notextended over top surface of the contact insulating layer; the tungstenlayer is not only filled within each the source-body contact trench butalso extended over top surface of the contact insulating layer; the gateelectrodes extended to a gate electrode contact area in which the gatetrenches having a greater trench width than those in the active area aswider gate electrode for electrically connecting to the gate metal, andthe source regions not disposed in the gate electrode contact area, andthe gate electrode spreading resistance built in between each the gateelectrode and the gate metal through the gate electrode contact area;the shielded electrodes extended to a shielded electrode contact area inwhich the gate trenches having a greater trench width than those in theactive area as wider shielded electrodes for electrically connecting tothe source metal, and the source regions not disposed in the shieldedelectrode contact area, and the shielded electrode spreading resistancebuilt in between each the shielded electrodes and the source metalthrough the source electrode contact area; the power semiconductordevice further comprising a termination area having multiple trenchedfloating gates with floating voltage, penetrating through the bodyregion and extending into the silicon layer, wherein the terminationarea does not have source regions; the power semiconductor devicefurther comprising a breakdown enhancement doped region below the bodyregion and above bottom of each the trenched floating gate; each of thetrenched floating gates comprising a single doped poly-silicon layerwith doping concentration same as the shielded electrodes; each of thetrenched floating gates comprising an upper and a lower dopedpoly-silicon layers insulated from each other by an inter-insulatinglayer.

This invention further disclosed a method of manufacturing a shieldedgate trench MOSFET comprising the steps of opening a plurality of gatetrenches in a silicon layer; forming a sacrificial oxide onto innersurface of the gate trenches and top surface of the silicon layer;depositing a first doped poly-silicon onto the sacrificial layer andetching it to keep the first poly-silicon within lower portion of thegate trenches in active area and gate electrode contact area, whileleaving the first doped poly-silicon fully filling into the gate trenchin shielded electrode contact area defined by a poly mask; etching backand removing the sacrificial oxide from the top surface of the siliconlayer not covered by the poly mask and from upper sidewalls of the gatetrenches in the active area and the gate electrode contact area, makingtop surface of the sacrificial oxide lower than top surface of theshielded electrodes in the active area and the gate electrode contactarea; removing away the poly mask; forming a gate oxide covering uppersidewalls of the gate trenches in the active area and the gate electrodecontact area and overlying top surface of the silicon layer; forming asecond doped poly-silicon layer filling in upper portion of the gatetrenches in the active area and the gate electrode contact area, whereinthe second doped poly-silicon having doping concentration equal to orhigher than the first doped poly-silicon; carrying out ion implantationto form body regions in upper portion of the silicon layer and extendingbetween every two adjacent of the gate trenches; carrying out ionimplantation to form source regions in upper portion of the body regiononly in the active area.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate exemplary embodiments of theinvention and together with the description serve to explain theprinciples of the invention. In the drawings:

FIG. 1A is a cross-sectional view showing a shielded gate trench MOSFETof prior art.

FIG. 1B is a top view showing the shielded gate trench MOSFET in FIG.1A.

FIG. 2 is a cross-sectional view showing a preferred embodiment of thepresent invention.

FIG. 3 is a cross-sectional view showing another preferred embodiment ofthe present invention.

FIG. 4 is a top view showing the shielded gate trench MOSFET accordingto the present invention.

FIG. 5 is a cross-sectional view showing another preferred embodiment ofthe present invention.

FIG. 6A is a cross-sectional view showing another preferred embodimentof the present invention.

FIG. 6B is a cross-sectional view showing another preferred embodimentof the present invention.

FIG. 6C is a cross-sectional view showing another preferred embodimentof the present invention.

FIG. 6D is a cross-sectional view showing another preferred embodimentof the present invention.

FIG. 6E is a cross-sectional view showing another preferred embodimentof the present invention.

FIGS. 7A˜7F are a serial of cross-sectional views for showing theprocessing steps for fabricating the shielded gate trench MOSFET asshown in FIG. 3.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 2 is a cross-sectional view showing a shielded gate trench MOSFET200 according to a preferred embodiment of the present invention. Theshielded gate trench MOSFET 200 is formed in a silicon layer, forexample an epitaxial layer 201 of a first conductivity type, heren-type, grown on top surface of an N+ semiconductor substrate 202 havingsame conductivity type with the N epitaxial layer 201 and padded by aback metal on rear side as drain metal 220. A plurality of gate trenches203 in active area, at least one gate trench 203′ and 203″ in gateelectrode contact area, and at least one gate trench 203″ in shieldedelectrode contact area are extending from top surface of the N epitaxiallayer 201 to a certain depth. Among those gate trenches, the gate trench203′ in the gate electrode contact area and the gate trench 203″ in theshielded electrode contact area each has greater trench width than thegate trenches 203 in the active area for wider electrode contact. Thegate trenches 203 in the active area each comprises a gate electrode 204in upper portion and a shielded electrode 205 in lower portion, whereinthe gate electrode 204 and the shielded electrode 205 is insulated fromeach other by an inter-electrode insulating layer 206. Along uppersidewalls of each the gate trench 203, a first gate oxide 207 is formedadjacent to the gate electrode 204 to insulate the gate electrode 204from n+ source regions 208 and P body regions 209 surrounding upperportion of the gate trench 203, wherein the P body regions are extendingbetween two adjacent of the gate trenches 203 and the n+ source regions208 are formed near top surface of the P body regions 209. Along bottomand lower sidewalls of each the gate trench 203, a second gate oxide 210is formed adjacent to the shielded electrode 205 to insulate theshielded electrode 205 from the N epitaxial layer 201. The gate trench203′ in the gate electrode contact area comprises a gate electrode 204′in upper portion and a shielded electrode 205′ in lower portion, whereinthe shielded electrode 205′ is insulated from the gate electrode 204′ byan inter-electrode insulating layer 206′, wherein the gate electrode204′ is insulated from the adjacent P body regions 209 by the first gateoxide 207 while the shielded electrode 205′ is insulated from theadjacent N epitaxial layer 201 by the second gate oxide 210. The gatetrench 203″ in the shielded electrode contact area comprises a sourceelectrode 211 which is insulated from the adjacent P body regions 208and the N epitaxial layer 201 by the second gate oxide 210. Within thegate electrode contact area and the shielded electrode contact area,there is no n+ source regions but only P body regions 209 extending inupper portion of the N epitaxial layer 201. Between every two adjacentof the gate trenches 203 in the active area, a source-body contacttrench 212 is formed penetrating through a contact insulating layer 213,the n+ source regions 208 and extending into the P body regions 208, anda P* anti-punch through region 214 is formed within the P body regions209 and surrounding bottom and sidewalls of the source-body contacttrench 212 below the n+ source regions 208. In the gate electrodecontact area, a gate electrode contact trench 215 is formed penetratingthrough the contact insulating layer 213 and extending into the gateelectrode 204′ in the gate trench 203′. In the shielded electrodecontact area, a source electrode contact trench 216 is formedpenetrating through the contact insulating layer 213 and extending intothe source electrode 211 in the gate trench 203″. A tungsten layer 217padded by a barrier layer of Ti/TiN or Co/TiN or Ta/TiN is formed notonly filled within the source-body contact trench 212, the sourceelectrode contact trench 216 and the gate electrode contact trench 215but also overlying top surface of the N epitaxial layer 201 to contactwith the n+ source regions 208, the P body regions 209, the sourceelectrode 211 and the gate electrode 204′, wherein the tungsten layer217 is patterned into two portions: one connected to a source metal 218padded by a resistance-reduction layer of Ti or Ti/TiN, and the otherconnected to a gate metal 219 padded by a resistance-reduction layer ofTi or TiN. What should be noticed is that, the gate electrode 204 ineach the gate trench 203 is connected to the gate electrode 204′ to beconnected to the gate metal 219 through a built in gate electrodespreading resistance Rg (as illustrated in FIG. 2) through the gateelectrode contact area, while the shielded electrode 205 in each thegate trench 203 is connected to the source electrode 211 to be connectedto the source metal 218 through a built in shielded electrode spreadingresistance Rs (as illustrated in FIG. 2) through the shielded electrodecontact area, wherein the gate electrode spreading resistance is lowerthan the shielded electrode spreading resistance.

FIG. 3 is a cross-sectional view showing a shielded gate trench MOSFET300 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET 200in FIG. 2 except that, the source-body contact trench 312 is penetratingthrough the contact insulating layer 313, the n+ source regions 318 andthe P body regions 319 and extending into the N epitaxial layer 301, andthe P* anti-punch through region 314 is formed surrounding bottom andsidewalls of the source-body contact trench 312 below the 0+ sourceregions 308, therefore, the P body regions 309 in the active area islocated between the P* anti-punch through doped region 314 and theadjacent gate trench 303.

FIG. 4 is a top view of the present invention showing that each theshielded electrode (underneath each the gate electrode, not shown) isconnected to the source electrode through the shielded electrodespreading resistance, wherein the source electrode is connected to thesource metal through the tungsten layer (not shown) filled into thesource electrode contact trench. It can be also seen that, each the gateelectrode is connected to the gate electrode in the wider gate trenchthrough the gate electrode spreading resistance, wherein the gateelectrode in the wider gate trench is connected to the gate metalthrough the tungsten layer (not shown) filled into the gate electrodecontact trench.

FIG. 5 is a cross-sectional view showing a shielded gate trench MOSFET400 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET,200 in FIG. 2 except that, the tungsten layer 417 is etched back to bekept only within each the source-body contact trench 412, the sourceelectrode contact trench 416 and the gate electrode contact trench 415.

FIG. 6A is a cross-sectional view showing a shielded gate trench MOSFET500 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET 200in FIG. 2 except that, the shielded gate trench MOSFET 500 furthercomprises a termination area including multiple of trenched gates 521having floating voltage, and the P body regions 509 are extended to thetermination area in upper portion of the N epitaxial layer 501 betweentwo adjacent of the trenched gates 521. Besides, the contact insulatinglayer 513 comprises a BPSG layer and an NSG layer beneath, and thesource-body contact trench 512 has greater trench width in the BPSGlayer than in the NSG layer. There is no source region in thetermination area.

FIG. 6B is a cross-sectional view showing a shielded gate trench MOSFET600 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET 300in FIG. 3 except that, the shielded gate trench MOSFET 600 furthercomprises a termination area including multiple of trenched gates 621having floating voltage, and the P body regions 609 are extended to thetermination area in upper portion of the N epitaxial layer 601 betweentwo adjacent of the trenched gates 621. Besides, the contact insulatinglayer 613 comprises a BPSG layer and an NSG layer beneath, and thesource-body contact trench 612 has greater trench width in the BPSGlayer than in the NSG layer.

FIG. 6C is a cross-sectional view showing a shielded gate trench MOSFET700 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET 600in FIG. 6B except that, the termination area of the shielded gate trenchMOSFET 700 further comprises a P′ breakdown enhancement doped region 722below each the P body region 709 and above bottom and each the trenchedgate 721 which has floating voltage to further enhance the breakdownvoltage.

FIG. 6D is a cross-sectional view showing a shielded gate trench MOSFET800 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET 600in FIG. 6B except that, each the trenched gate in the termination areacomprises a gate electrode in upper portion and a shielded electrode inlower portion, which has the same structure as the gate trench in theactive area.

FIG. 6E is a cross-sectional view showing a shielded gate trench MOSFET900 according to another preferred embodiment of the present inventionwhich has a similar configuration to the shielded gate trench MOSFET 800in FIG. 6D except that, the termination area of the shielded gate trenchMOSFET 900 further comprises a P′ breakdown enhancement doped region 922below each the P body region 909 and above bottom and each the trenchedgate which has floating voltage to further enhance the breakdownvoltage.

FIGS. 7A to 7F are a serial of exemplary steps that are performed toform the preferred shielded gate trench MOSFET 300 in FIG. 3. In FIG.7A, an N epitaxial layer 301 is grown on an N+ substrate 302. A trenchmask (not shown) is applied to open a plurality of gate trenchesextending from top surface of the N epitaxial layer 301, among thosegate trenches including: a plurality of gate trenches 303 in the activearea; at least one gate trench 303′ in gate electrode contact area andat least one gate trench 303″ in shielded electrode contact area.

In FIG. 7B, a sacrificial oxide layer 325 is grown along inner surfaceof those gate trenches formed in FIG. 7A and overlying the top surfaceof the N epitaxial layer 301. Then, a first doped poly-silicon layer isfirst deposited filling in those gate trenches and covering the topsurface of the N epitaxial layer 301 and then processed by poly-siliconCMP (Chemical Mechanical Polishing). After that, a poly mask is appliedonto the first doped poly-silicon layer and a step of dry poly-siliconetching back is performed to remove portion of the first dopedpoly-silicon layer away from the upper portion of the gate trenches 303in the active area and the gate trench 303′ in the gate electrodecontact area to form shielded electrode 305 and 305′ respectively in thegate trenches 303 and 303′. Therefore, the doped poly-silicon layer inthe gate trench 303″ is fully remained to act as the source electrode311.

In FIG. 7C, a step of the sacrificial oxide time etching back isperformed to remove the sacrificial oxide 325 away from upper sidewallsof the gate trenches 303 and 303′ and the top surface of the N epitaxiallayer 301 not covered by the poly mask as illustrated in FIG. 2, makingtop surface of the sacrificial oxide 325 lower than top surface of theshielded electrode 305 and 305′ in gate trenches 303 and 303′,respectively to act as a second gate oxide layer surrounding lowersidewalls of bottoms of the gate trenches 303 and 303′, whilesurrounding sidewall and bottom of the gate trench 303″. And then, thepoly mask as illustrated in FIG. 7B is removed away.

In FIG. 7D, a gate oxidation is carried out to form gate oxide layercovering the top surface of the sacrificial oxide 325 and the shieldedelectrodes 305 and 305′ to serve as the inter-electrode insulating layer306 and 306′, as well as along upper sidewalls of the gate trenches 303and 303′ and overlying the top surface of the N epitaxial layer 301 toact as the first gate oxide 307. Then, a second doped poly-silicon layeris deposited onto the inter-electrode insulating layer 306 and 306′ andthe first gate oxide 307. After that, the second doped poly-siliconlayer is processed by CMP and doped poly etching back to form the gatetrench 304 and 304′ filling within the upper portion of the gate trench303 and 303′, respectively. Next, a P body ion implantation and adriving in step are successively carried out to form the P body region309 extending in upper portion of the N epitaxial layer 301 betweenevery two adjacent of the gate trenches 303, 303′ and 303″. Then, afterapplying a source mask (not shown), an n+ source ion implantation iscarried out optionally followed by a driving in step to form the n+source region 308 only disposed in upper portion of the P body region309 in the active area.

In FIG. 7E, an oxide is deposited onto top surface of the shielded gatetrench MOSFET to serve as the contact insulating layer 313. Then, afterapplying a contact mask (not shown), a step of dry contact oxide etchingand a step of dry silicon etching are successively carried out to form aplurality of contact trenches, including: a source-body contact trench312 penetrating through the contact insulating layer 313, the n+ sourceregion 308 and extending into the P body region 309 between every twoadjacent of the gate trench 303 in the active area; a gate electrodecontact trench 315 penetrating through the contact insulating layer 313and extending into the gate electrode 304′ in the gate electrode contactarea; a source electrode contact trench 316 penetrating through thecontact insulating layer 313 and extending into the source electrode 311in the shielded electrode contact area. Next, a BF2 zero degree ionimplantation and a BF2 angle ion implantation are successively carriedout and followed by a RTA (rapid thermal annealing) process to form theanti-punch through region 314 in the P body region 309 and surroundingbottom and sidewalls of the source-body contact trench 312 below the n+source regions 308.

In FIG. 7F, after depositing a barrier layer of Ti/TiN or Co/TiN orTa/TiN covering top surface of the contact insulating layer 313 andalong inner surface of the source-body contact trench 312, the gateelectrode contact trench 315 and the source electrode contact trench316, a tungsten layer 317 is deposited onto the barrier layer and thenoptionally etched back to keep the tungsten layer 317 remaining only inthose contact trenches. Then, onto the barrier layer and the tungstenlayer 317, a front metal Al alloys 318 padded by a resistance-reductionlayer Ti or Ti/TiN is deposited and then be patterned by a metal mask(not shown) and metal etching process. Next, after grinding the backsideof the N+ substrate 302, a back metal 320 is deposited whereon as drainmetal.

Although the present invention has been described in terms of thepresently preferred embodiments, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alternationsand modifications will no doubt become apparent to those skilled in theart after reading the above disclosure. Accordingly, it is intended thatthe appended claims be interpreted as covering all alternations andmodifications as fall within the true spirit and scope of the invention.

1. A power semiconductor device comprising: a plurality of gate trenchesextending into a silicon layer of a first conductivity type; a gateelectrode disposed in upper portion of each of said gate trenches and ashielded electrode disposed in lower portion of each of said gatetrenches, wherein said gate electrode and said shielded electrodeinsulated from each other by an inter-electrode insulating layer; saidgate electrode and said shielded electrode are doped poly-silicon layerswherein said gate electrode having doping concentration equal to orhigher than said shielded electrode; said gate electrode connected to agate metal through a gate electrode spreading resistance and saidshielded electrode connected to a source metal through a shieldedelectrode spreading resistance; and said upper portion of said gatetrenches surrounded by source regions of said first conductivity typeand body regions of a second conductivity type in active area.
 2. Thepower semiconductor device of claim 1, wherein said gate electrodespreading resistance is less than said shielded electrode spreadingresistance.
 3. The power semiconductor device of claim 1 furthercomprising a first gate oxide along sidewalls of said gate electrode anda second gate oxide surrounding bottom and sidewalls of said shieldedelectrode in each of said gate trenches, wherein said second gate oxidehaving oxide thickness thicker than said first gate oxide.
 4. The powersemiconductor device of claim 1 further comprising a plurality ofsource-body contact trenches formed between two adjacent of said gatetrenches and penetrating through a contact insulating layer and saidsource regions and extending into said body regions.
 5. The powersemiconductor device of claim 4, wherein said contact insulating layeris a single oxide layer.
 6. The power semiconductor device of claim 4,wherein said contact insulating comprises a BPSG layer and an NSG layerbeneath, wherein said source-body contact trenches have greater trenchwidth in said BPSG layer than in the NSG layer.
 7. The powersemiconductor device of claim 1 further comprising a plurality ofsource-body contact trenches formed between two adjacent of said gatetrenches and penetrating through a contact insulating layer, said sourceregions and said body regions and extending into said silicon layer. 8.The power semiconductor device of claim 4 further comprising a tungstenlayer padded by a barrier layer filled into each said source-bodycontact trench for contacting said source regions and said body regionsalong sidewalls of said source-body contact trenches, and said tungstenlayer electrically connected to said source metal.
 9. The powersemiconductor device of claim 7 further comprising a tungsten layerpadded by a barrier layer filled into each said source-body contacttrench for contacting said source regions and said body regions alongsidewalls of said source-body contact trenches, and said tungsten layerelectrically connected to said source metal.
 10. The power semiconductordevice of claim 4 further comprising an anti-punch through region ofsaid second conductivity type surrounding sidewall and bottom of eachsaid source-body contact trench below said source region.
 11. The powersemiconductor device of claim 7 further comprising an anti-punch throughregion of said second conductivity type surrounding sidewall and bottomof each said source-body contact trench below said source region. 12.The power semiconductor device of claim 8, wherein said tungsten layeris only filled within each said source-body contact trench but notextended over top surface of said contact insulating layer in claims 3and
 4. 13. The power semiconductor device of claim 8, wherein saidtungsten layer is not only filled within each said source-body contacttrench but also extended over top surface of said contact insulatinglayer in claims 3 and
 4. 14. The power semiconductor device of claim 9,wherein said tungsten layer is only filled within each said source-bodycontact trench but not extended over top surface of said contactinsulating layer in claims 3 and
 4. 15. The power semiconductor deviceof claim 9, wherein said tungsten layer is not only filled within eachsaid source-body contact trench but also extended over top surface ofsaid contact insulating layer in claims 3 and
 4. 16. The powersemiconductor device of claim 1, wherein said gate electrodes extendedto a gate electrode contact area in which said gate trenches having agreater trench width than those in said active area as wider gateelectrode for electrically connecting to said gate metal, and saidsource regions not disposed in said gate electrode contact area, andsaid gate electrode spreading resistance built in between each said gateelectrode and said gate metal through said gate electrode contact area.17. The power semiconductor device of claim 1, wherein said shieldedelectrodes extended to a shielded electrode contact area in which saidgate trenches having a greater trench width than those in said activearea as wider shielded electrodes for electrically connecting to saidsource metal, and said source regions not disposed in said shieldedelectrode contact area, and said shielded electrode spreading resistancebuilt in between each said shielded electrode and said source metalthrough said source electrode contact area.
 18. The power semiconductordevice of claim 1 further comprising a termination area having multipletrenched floating gates with floating voltage, penetrating through saidbody region and extending into said silicon layer wherein saidtermination area does not have source regions.
 19. The powersemiconductor device of claim 18 further comprising a breakdownenhancement doped region of said second conductivity type below saidbody region and above bottom of each said trenched floating gate. 20.The power semiconductor device of claim 18, wherein each of saidtrenched floating gates comprising a single doped poly-silicon layerwith doping concentration same as said shielded electrodes.
 21. Thepower semiconductor device of claim 18, wherein each of said trenchedfloating gates comprising an upper and a lower doped poly-silicon layersinsulated from each other by an inter-electrode insulating layer.
 22. Amethod for manufacturing a shielded gate trench MOSFET comprising thesteps of: opening a plurality of gate trenches in a silicon layer;forming a sacrificial oxide onto inner surface of said gate trenches andtop surface of said silicon layer; depositing a first doped poly-silicononto said sacrificial layer and etching it to keep said firstpoly-silicon within lower portion of said gate trenches in active areaand gate electrode contact area, while leaving said first dopedpoly-silicon fully filling into said gate trench in shielded electrodecontact area defined by a poly mask; etching back and removing saidsacrificial oxide from the top surface of said silicon layer not coveredby the poly mask and from upper sidewalls of said gate trenches in saidactive area and said gate electrode contact area, making top surface ofsaid sacrificial oxide lower than top surface of said shieldedelectrodes in said active area and said gate electrode contact area;removing away said poly mask; forming a gate oxide covering uppersidewalls of said gate trenches in said active area and said gateelectrode contact area and overlying top surface of said silicon layer;forming a second doped poly-silicon layer filling in upper portion ofsaid gate trenches in said active area and said gate electrode contactarea, wherein said second doped poly-silicon having doping concentrationequal to or higher than said first doped poly-silicon; carrying out ionimplantation to form body regions in upper portion of said silicon layerand extending between every two adjacent of said gate trenches; carryingout ion implantation to form source regions in upper portion of saidbody region only in said active area.
 23. The method of claim 22 furthercomprising the steps of: depositing a contact insulating layer; applyinga contact mask; forming a source-body contact trench penetrating throughsaid contact insulating layer, said source region and extending intosaid body region between every two adjacent of said gate trenches insaid active area; and carrying out ion implantation to form ananti-punch through region in said body region and surrounding bottom andsidewalls of said source-body contact trench below said source region.24. The method of claim 22 further comprising the steps of: depositing acontact insulating layer; applying a contact mask; forming a source-bodycontact trench penetrating through said contact insulating layer, saidsource region, said body region and extending into said silicon layerbetween every two adjacent of said gate trenches in said active area;and carrying out ion implantation to form an anti-punch through regionsurrounding bottom and sidewalls of said source-body contact trenchbelow said source region.
 25. The method of claim 23 further comprisingforming a tungsten layer padded by a barrier layer filling into saidsource-body contact trench and covering to surface of said contactinsulating layer.
 26. The method of claim 24 further comprising forminga tungsten layer padded by a barrier layer filling into said source-bodycontact trench and covering to surface of said contact insulating layer.27. The method of claim 26, wherein said tungsten layer is etched backaway from top surface of said contact insulating layer.